Implementation and Performance Analysis of Kaiser and Hamming Window Techniques on FPGA

Considering the importance of real time filtering, a comparison was done between two prominent window techniques known for digital filtering. A 16 tap digital band pass FIR filter is designed for each design technique (Kaiser and Hamming) and implemented over FPGA. The Simulink model of the filter confirms the correctness and other properties of the digital filter. Further a hardware descriptive code (VHDL) is generated for the designed filter which then will be loaded on to the FPGA. The VHDL code is speed optimized. The VHDL code is simulated and synthesized in Xilinx ISE. Further the performance analysis is done on FPGA to determine the applicability of the filter.